A dynamic random access memory (DRAM) has a bitcell for storing a bit as either a one or a zero. A DRAM bitcell can be relatively simple in design compared to the bitcells of other types of computer memories. In one DRAM bitcell design, the bitcell comprises primarily a capacitor which stores an electrical charge, the level of which represents either a one or zero stored in the bitcell. As a consequence, DRAM bitcells may frequently take up less space than other bitcell designs.
The bitcell also typically includes a cell switch transistor which in an off state, inhibits discharge of the charge stored on the bitcell capacitor. In the on state, the switching transistor connects the bitcell capacitor to read/write circuitry which can read the charge level stored on the capacitor and hence read the bit value stored in the bitcell. The cell switch transistor also connects the bitcell capacitor to read/write circuitry which can store charge on the bitcell capacitor at a level which “writes” a bit value into the bitcell. Access to a DRAM bitcell for read and write operations may frequently be carried out more quickly than many other bitcell designs.
However, even in the off state of the cell switch transistor, the charge stored on the storage capacitor of the DRAM bitcell tends to leak from the bitcell such that the stored charge level tends to decay over time. If the bitcell is not read before the charge level decays to a certain degree, such charge level decay can cause data loss and errors in reading the bit values stored in the bitcells.
To prevent such errors and loss, many DRAM designs include refresh circuitry which periodically refreshes the charge levels stored in the bitcells. Thus, even if there is a long delay before a bitcell is read, the refresh circuitry can maintain the stored charge level of the bitcell to preserve the bit data value of the bitcell until the data is needed. However, the refresh operations consume power which can shorten battery life in mobile applications.
In many DRAM designs, the refresh operation of a bitcell includes reading the bitcell in a sense phase of a bitcell refresh cycle. The bit data value read during the sense phase of the refresh cycle is often latched because the read operation usually destroys the charge level stored in the bitcell. The latched bit data value is then written back into the bitcell in a restoration phase of the refresh cycle, restoring the charge level to a level representing the read bit data value read from the bitcell, and completing the refresh cycle for that bitcell. The refresh cycle is periodically repeated to maintain the stored charge at a minimum level to ameliorate data loss and read errors.
In some devices, the refresh operations are controlled internally. Such internally controlled refresh is often referred to as “self-refresh.” In order to decrease the power consumed by self-refresh operations (often referred to as IDD6 or Self-Refresh Power), various approaches have been proposed. In one such approach referred to as “partial refresh,” all bitcells are not necessarily refreshed. For example, the refresh operations may be restricted to those bitcells containing the more important data which is to be retained while refresh operations are withheld from bitcells containing less important data which can be discarded. However, determining which data can be safely discarded can be problematical.
Another approach often referred to as “adaptive self-refresh” stores a data retention time value for each group of bitcells, such as a word line of bitcells of a bank of bitcells. For a word line of bitcells having a longer retention time value, the duration of time between refresh operations may be extended for a longer period of time as compared to a word line of bitcells having a shorter retention time value. For those bitcells of a word line for which the duration of time between refresh operations is extended, refresh power may be reduced. However, such schemes may have a large overhead cost in circuit complexity and die space consumed.
It is noted that the process technology for DRAM memory continues to shrink the DRAM bitcell and die size aggressively. As the DRAM dimensions shrink, the data retention periods tend to shrink as well. For example, for one DRAM memory design, the retention period has recently shrunk from 64 milliseconds (ms) to 32 ms. As a result, the frequency of refresh operations and the power consumed by such refresh operations, tend to increase as retention periods decrease.
Moreover, advances in process technology have permitted the memory density on a die to increase dramatically from 4 gigabytes (Gb), for example, to 8 Gb, 12 Gb and more. As a consequence the number of bitcells per die requiring refreshing and the associated power to refresh those additional cells, continue to increase. For example, if the number of refresh operations remains the same, the number of bitcells refreshed in each refresh operations will increase to accommodate the greater number of bitcells. Conversely, if the number of bitcells refreshed in each refresh operation remain the same, the number of refresh operations will increase to accommodate the increased number of bitcells. In either case, refresh power tends to increase as bitcell density increases.